Field of the Present Disclosure
The present disclosure relates to a wafer grinding device, and, more particularly, to a wafer grinding device to suppress wafer deformation due to rotation of a grinding wheel contacting a wafer surface when grinding the wafer surface.
Discussion of the Related Art
Generally, a silicon single crystal wafer used to produce electronics such as semiconductor device, etc. Furthermore, such a silicon single crystal wafer according to the present invention can be manufactured by the following manufacturing method. However, the present invention is not restricted thereto.
First, a silicon single crystal ingot is prepared. A general ingot can be prepared as this silicon single crystal ingot, and this ingot can be grown based on, e.g., the Czochralski method.
Then, the prepared silicon single crystal ingot is sliced to provide a plurality of sliced substrates. This slicing can be performed by a general method, and slicing can be performed by using a cutting device such as an inner diameter slicer or a wire saw.
Furthermore, at least one of lapping, etching, and polishing is performed with respect to the plurality of obtained sliced substrates to provide substrates. The lapping, the etching, and the polishing can be performed under general conditions, and they can be appropriately selected in accordance with a specification of a silicon single crystal wafer to be manufactured.
Before the lapping and polishing and after the slicing, the silicon single crystal wafer may be further grinded to control the thickness and flatness. This process may be referred to as a grinding process.
The grinding process may satisfy the very high precision of flatness required for the semiconductor device with a high integration degree. In this connection, the wafer flatness may be defined by a SBIR (site backside ideal range) including a TTV (total thickness variation) indicating a difference between maximum and minimum wafer thicknesses, and a LTV (local thickness variation). As a design rule of the semiconductor device gets finer, it may be difficult to obtain a high quality wafer to meet the TTV and SBIR related requirements only using the lapping and polishing process. Thus, in order to meet the wafer flatness requirements, the grinding process may be further needed.
FIG. 1 illustrates a silicon wafer grinding device for grinding the wafer. As shown in FIG. 1, the conventional wafer grinding device includes a spindle 10, a grinding wheel 11 coupled to a bottom of the spindle 10 and configured to rotate, and a chuck table 15 configured to suction the wafer.
When the wafer W is loaded on the chuck table 15, the chuck table 15 suctions the wafer W using a vacuum pressure and enable the suctioned wafer W to rotate in a given rate. When the spindle 10 spaced from and above the chuck table 15 at a predetermined distance rotates and descends, the spindle 10 may contact the wafer and grind the wafer using the grinding wheel 11 coupled thereto.
The grinding wheel 11 include a rotatable grinding body 12, and grinding teeth 13 coupled to a bottom edge of the grinding body 12. The previous grinding wheel 11 may be configured such that the grinding teeth 13 made of a diamond are spaced from each other at a predetermined distance and are bonded to the body 12 via an adhesive, and protrude downwards from the body 12. In this way, when the chuck table 15 suctions the silicon wafer, and the spindle 10 rotates in a high speed, the previous grinding wheel 11 rotates to grind the wafer surface using the grinding teeth 13 thereof.
However, when grinding the wafer using the grinding wheel 11, a hot heat may be created in the grinding wheel 11 and wafer W due to the high speed rotation. This heat may be accumulated in the grinding wheel 11, thereby to increase a working load during the grinding process, and to cause the wafer burning, etc.
Further, a grinding byproduct may be attached onto fine holes in a working face of each of the grinding teeth 13, to deteriorate a grinding force of the grinding teeth 13. This may be referred to as a hole-blocked event. This event may increase an working time to achieve a wafer target thickness. This may lead to a lowered yield of the wafer. Further, this may lead to poor wafer flatness and nano-quality.